Present complementary metal oxide semiconductor (CMOS) dynamic random access memory (DRAM) circuits are frequently used for main memory in a variety of system applications, e.g., laptop and notebook computer systems which are battery powered. These battery powered applications impose practical limitations such as speed, power, feature size, and reliability on dynamic random access memory design. Optimal performance of a system depends on an effective balance of these factors in the design. Current dynamic random access memory designs minimize operating voltage to maximize reliability as feature sizes and oxide thicknesses decrease.
A reduction in operating voltage effectively reduces power consumption and is beneficial to many aspects of dynamic random access memory reliability. It is constrained, however, by desired operating speed, a function of internal operating voltage, and a need for compatibility with the operating voltage of existing system applications. An on-chip voltage regulator can reduce dynamic random access memory internal operating voltage and thereby maximize reliability. It also maintains compatibility with the operating voltage of existing system applications. An additional benefit of an on-chip voltage regulator is that it can maintain a stable internal chip voltage over relatively large variations of an external voltage. Even though dynamic random access memory may be subjected to relatively large variations of external voltage, internal voltage changes are minimized and operating speed will remain stable.
An effective on-chip voltage regulator responds to a variation in circuit load requirements so that circuit operation and speed are not compromised. Additionally, power consumption of the voltage regulator should be minimized so that such power consumption does not overcome other advantages of on-chip voltage regulation. Thus, good voltage regulator design becomes increasingly difficult with greater variation in circuit load requirements. This is particularly true in a dynamic random access memory where an on-chip regulator may be required to maintain a relatively constant internal voltage while variations in peak load current exceed three orders of magnitude.
A major component of power consumption in a dynamic random access memory is due to charging bitline capacitance during a read or refresh cycle. A typical dynamic random access memory read operation destructively reads a datum from a memory cell then restores the datum. A 4 MB (4,194,304 memory cells) dynamic random access memory that is completely refreshed by a cycle of 1K (1024) addresses simultaneously reads about 4K (4096) memory cells for each of the 1K addresses. Each of the memory cells from which the datum is simultaneously read is connected to a different bitline and sense amplifier. Thus, 4K sense amplifiers are simultaneously activated to amplify or sense small signals produced by the memory cells. Each sense amplifier drives one of two complementary bitlines from a bitline reference voltage to the potential of the internal power supply. The other complementary bitline is driven to ground. Peak load current may increase from less than 100 .mu.A prior to sensing to greater than 100 mA when the 4K sense amplifiers are simultaneously activated during sensing.
Conflicting issues of power supply regulator power consumption and stable power supply regulation for wide variations in circuit load requirements are discussed in Yoshinobu Nakagome et al, Circuit Techniques for 1.5-3.6 V Battery-Operated 64-Mb DRAM, IEEE Journal of Solid State Circuits, vol. 26, No. 7, 1003, 1007 (1991). Their voltage down converter (VDC) consists of a current-mirror differential amplifier, an output stage, and a voltage switch (SW). "[T]he VDC is enabled when V.sub.cc &gt;1.65 V . . . and the SW is enabled when V.sub.cc &lt;1.65 V." Nakagome et al give two reasons "why the SW circuit is used in the low operating voltage region." First, the "driving capability of Q8 is comparatively low when V.sub.cc is decreased." The SW circuit provides more drive than the output stage for the differential amplifier because "[t]he gate width of Q9 is about three times larger than Q8." Second, the SW circuit saves "operating power of the VDC when the supply voltage is low and VCC can be directly applied."
There are two notable concerns with the teaching of Nakagone et al. First, the gate width of output drive transistor Q8 affects the response time of the current-mirror differential amplifier. Any increase in transistor sizes of the current-mirror differential amplifier increases power consumption. Second, the magnitude of power consumption of the VDC and, in particular, the current-mirror differential amplifier is a significant liability. Nakagone et al use the regulator for adequate response time in the high voltage operating region and accept the undesirable power consumption of the VDC circuit. In the low voltage operating region, where power consumption is less of a concern, the SW circuit is used to eliminate power consumption by the VDC.